The present invention is an improvement over the circuit shown on Applicant's U.S. Pat. No. 4,937,840 issued to Applicant William Hotine on Jun. 26, 1990. This patent describes a circuit in which serial binary digits having a clock frequency the same as the sine wave carrier frequency are encoded as brief phase deviations at the start of a cycle of carrier frequency for a digital one, digital zero being the normal wave form. The clock frequency is encoded by a brief phase deviation at the middle of each cycle of the carrier frequency. One binary digit is encoded per cycle of the carrier frequency by this circuit.